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SX1231
WIRELESS & SENSING PRODUCTS
DATASHEET
RegIrqFlags2
(0x28)
7
6
5
FifoFull
FifoNotEmpty
FifoLevel
r
r
r
0
0
0
Set when FIFO is full (i.e. contains 66 bytes), else
cleared.
Set when FIFO contains at least one byte, else cleared
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold , else cleared.
4
FifoOverrun
rwc
0
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The
FIFO then becomes immediately available for the next
transmission / reception.
3
PacketSent
r
0
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx.
2
PayloadReady
r
0
Set in Rx when the payload is ready (i.e. last byte
received and CRC, if enabled and CrcAutoClearOff is
cleared , is Ok). Cleared when FIFO is empty.
1
CrcOk
r
0
Set in Rx when the CRC of the payload is Ok. Cleared
when FIFO is empty.
0
LowBat
rwc
-
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set by the user.
RegRssiThresh
(0x29)
RegRxTimeout1
7-0
7-0
RssiThreshold
TimeoutRxStart
rw
rw
0xE4
*
0x00
RSSI trigger level for Rssi interrupt :
- RssiThreshold / 2 [dBm]
Timeout interrupt is generated TimeoutRxStart *16*T bit
(0x2A)
after switching to Rx mode if Rssi interrupt doesn’t occur
(i.e. RssiValue > RssiThreshold)
0x00: TimeoutRxStart is disabled
RegRxTimeout2
7-0
TimeoutRssiThresh
rw
0x00
Timeout interrupt is generated TimeoutRssiThresh *16*T bit
(0x2B)
after Rssi interrupt if PayloadReady interrupt doesn’t
occur.
0x00: TimeoutRssiThresh is disabled
Rev. 7 - June 2013
Page 72
www.semtech.com
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